1. Field of the Invention
The present invention relates to a semiconductor device comprising a memory cell array in which bit lines are hierarchized.
2. Description of Related Art
In recent years, semiconductor devices such as DRAM have increased in capacity and decreased in size, and with this, memory cell arrays in which bit lines are hierarchized into global bit lines and local bit lines tend to be used. In such memory cell arrays, a plurality of local bit lines are arranged corresponding to each one of the global bit lines, and a plurality of memory cells are arranged corresponding to each of the local bit lines, thereby shortening the line length of each of the local bit lines. Further, by providing many hierarchical switches that control electrical connections between the global bit line and the local bit lines, data of a selected memory cell can be transmitted from one of the local bit lines to the global bit line through a hierarchical switch. For example, Patent Reference 1 discloses a specific example of a semiconductor device comprising a memory cell array having a hierarchical bit line structure.    [Patent Reference 1] Japanese Patent Application Laid-open No. 2011-154754
In the semiconductor devices that have decreased in size, it is generally desirable to sufficiently remove initial failure by applying voltage stresses to the memory cell array at a stage of a wafer test before product shipment. The voltage stresses can be applied to the above-described hierarchical memory cell array by utilizing precharge transistors provided on the local bit lines so as to supply a desired potential in a state where all hierarchical switches are turned off. For example, assuming a configuration of the semiconductor device disclosed in the Patent Reference 1, two adjacent local bit lines along an extending direction of one global bit line are electrically isolated from each other with a short distance, and thereby it is particularly important to expose the failure occurring in manufacturing processes by applying a voltage stress between them. However, restriction of circuit configuration shown in the Patent Reference 1 makes it difficult to supply potentials different from each other to the two adjacent local bit lines along the extending direction of the one global bit line. In this manner, the above conventional hierarchical memory cell array poses a problem that the voltage stress cannot be effectively applied between the adjacent local bit lines by the test before product shipment.